A low-complexity LDPC decoder architecture for WiMAX applications

In this paper, we present a low-complexity decoder architecture for WiMAX low-density parity-check (LDPC) codes based on a unified task processor. Memory access is accomplished through routing networks with fixed interconnections and memory address generators, which are quite simple due to the quasi-cyclic structure of the LDPC codes. In order to increase the decoding throughput, the check-node and variable-node operations are performed concurrently, and a modified layered decoding is employed. Based on this architecture, we implemented a full-mode WiMAX codec in a 90-nm process. This codec achieves an encoding (decoding) throughput of 960 Mb/s (240 Mb/s) and occupies an area of 0.679 mm².