A low-complexity LDPC decoder architecture for WiMAX applications

Author

Wang, Yu-Luen ; Ueng, Yeong-Luh ; Peng, Chian-Lien ; Yang, Chung-Jay

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2011

fDate

25-28 April 2011

Firstpage

1

Lastpage

4

Abstract

In this paper, we present a low-complexity decoder architecture for WiMAX low-density parity-check (LDPC) codes based on a unified task processor. Memory access is accomplished through routing networks with fixed interconnections and memory address generators, which are quite simple due to the quasi-cyclic structure of the LDPC codes. In order to increase the decoding throughput, the check-node and variable-node operations are performed concurrently, and a modified layered decoding is employed. Based on this architecture, we implemented a full-mode WiMAX codec in a 90-nm process. This codec achieves an encoding (decoding) throughput of 960 Mb/s (240 Mb/s) and occupies an area of 0.679 mm².

Keywords

WiMax; decoding; parity check codes; storage allocation; telecommunication network routing; LDPC codes; WiMAX applications; WiMAX low-density parity-check codes; check-node; decoding throughput; encoding throughput; fixed interconnections; full-mode WiMAX codec; low-complexity LDPC decoder architecture; low-complexity decoder architecture; memory access; memory address generators; modified layered decoding; quasi-cyclic structure; routing networks; unified task processor; variable-node operations; Decoding; Generators; Parity check codes; Prototypes; Routing; Throughput; WiMAX; LDPC codes; WiMAX; channel decoder;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on

Conference_Location

Hsinchu

ISSN

Pending

Print_ISBN

978-1-4244-8500-0

Type

conf

DOI

10.1109/VDAT.2011.5783633

Filename

5783633