Title :
Prospects and implementation of Non-DVFS dynamic thermal management techniques
Author :
Vora, Pritesh ; Choudhary, Masud H.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Chicago, Chicago, IL, USA
fDate :
May 30 2010-June 2 2010
Abstract :
Non-DVFS dynamic thermal management (DTM) techniques like fetch-throttling, rename-throttling and register-file occupancy-throttling have some favorable features compared to dynamic voltage and frequency scaling (DVFS) technique for the potential use in multi-core chip designs. This paper presents an approach to implement these non-DVFS techniques in a processor architecture. This analysis and implementation provides a way to evaluate the performance of these DTM techniques in multi-core chips and resolve some implementation restrictions. The combination of CPU and memory bound workloads are used to simulate the proposed implementation. The observations are verified by using RTL level simulations in Verilog for power estimation and fuctionality check.
Keywords :
microprocessor chips; CPU workload; DTM technique; RTL level simulations; Verilog; dynamic voltage-frequency scaling technique; fetch-throttling technique; memory bound workloads; multicore chip designs; nonDVFS dynamic thermal management techniques; power estimation; processor architecture; register-file occupancy-throttling technique; rename-throttling technique; Computational modeling; Delay; Dynamic voltage scaling; Engineering management; Frequency; Microprocessors; Registers; Temperature sensors; Thermal engineering; Thermal management;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537085
