Merged Digitally Controlled Oscillator and Time to Digital Converter for TV band ADPLL

Author

Altabban, Wissam ; Desgreys, Patricia ; Petit, Hervé ; Ben Kalaia, Karim ; Du Roscoat, Laure Rolland

Author_Institution

Telecom ParisTech, Inst. Telecom, Paris, France

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

1987

Lastpage

1990

Abstract

In this paper we present a merged Digitally Controlled Oscillator DCO and Time To Digital Converter TDC architecture. The DCO is a nine-stage interpolative ring made by NOR cells. It is designed for TV applications and it is implemented in 65nm CMOS process. The oscillator has a large frequency range, from 50MHz to 500MHz, and a 28 × 39/μm² core area. It consumes 1mA from 1.2V power supply, and it has -120dBc/Hz@5MHz phase noise for 420 MHz carrier frequency. The oscillator states are directly used to measure the delay between input and output clocks. The resulting TDC is compact, very economic in power consumption and it has a resolution that is equal to 1/18 of the oscillation period. The DCO and the TDC are used in an All Digital Phase Locked Loop ADPLL.

Keywords

CMOS integrated circuits; NOR circuits; analogue-digital conversion; phase locked loops; television equipment; CMOS process; NOR cell; TV band ADPLL; all digital phase locked loop; current 1 mA; digitally controlled oscillator; frequency 50 MHz to 500 MHz; interpolative ring; size 65 nm; time-to-digital converter; voltage 1.2 V; CMOS process; Clocks; Delay; Digital control; Frequency; Oscillators; Phase noise; Power generation economics; Power supplies; TV;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537087

Filename

5537087