Title :
Design and layout of a high ESD performance NPN structure for submicron BiCMOS/bipolar circuits
Author :
Chen, Julian Z. ; Zhang, Xin Yi ; Amerasekera, Ajith ; Vrotsos, Tom
Author_Institution :
Mixed Signal Products, Texas Instrum. Inc., Dallas, TX, USA
fDate :
April 30 1996-May 2 1996
Abstract :
This paper presents a high ESD performance NPN protection structure for advanced submicron BiCMOS and Bipolar processes. Using a Zener trigger circuit and a specific multi-emitter layout technique, this paper successfully demonstrates an optimal protection structure to meet the requirements imposed on advanced submicron circuit applications. The protection circuit has a low trigger voltage as well as a low capacitance load and does not add any series resistance.
Keywords :
BiCMOS integrated circuits; VLSI; bipolar integrated circuits; circuit optimisation; electrostatic discharge; integrated circuit design; trigger circuits; ESD performance; NPN structure; Zener trigger circuit; low capacitance load; multi-emitter layout technique; optimal protection structure; submicron BiCMOS circuits; submicron bipolar processes; trigger voltage; Avalanche breakdown; BiCMOS integrated circuits; Diodes; Electrostatic discharge; Fingers; Instruments; Low voltage; Parasitic capacitance; Protection; Pulse measurements;
Conference_Titel :
Reliability Physics Symposium, 1996. 34th Annual Proceedings., IEEE International
Conference_Location :
Dallas, TX, USA
Print_ISBN :
0-7803-2753-5
DOI :
10.1109/RELPHY.1996.492124
