Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology

This paper proposes a compiler-in-the-loop exploration framework during architectural DSP synthesis. We extend the conventional design space, considering code level transformations together with architectural level optimizations and their impact on the scheduled datapath. We show that the proposed methodology explores the design space more globally in comparison with existing methods. New trade-off points are revealed and Pareto curve shifting towards higher quality design solutions is performed.