Title :
Technology remapping for engineering change with wirelength consideration
Author :
Hung, Jui-Hung ; Yeh, Yao-Kai ; Tseng, Yung-Sheng ; Hsieh, Tsai-Ming
Author_Institution :
Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chungli, Taiwan
fDate :
May 30 2010-June 2 2010
Abstract :
In this paper, we present an efficient approach to make functional change by using spare cells efficiently. The proposed approach includes two main steps (1) technology remapping and (2) spare cell selection. In technology remapping step, resource constraints will be considered to find a set of proper cells for remapping with examining resources exhaustively. In spare cell selection, we regard this problem as a question of resource allocation, the goal is to simultaneously select the suitable spare cells to achieve the functional changes and minimize the wirelength increases. We modify the matching algorithm to solve the spare cell selection with the goal of minimizing the increase in wire length, and use two wiring cost estimate methods to improve the wiring cost measurement of accuracy. Experimental results based on nine industry benchmarks show that there is 1% bias between the wiring cost our approach estimated and the actual wiring cost.
Keywords :
VLSI; integrated circuit design; resource allocation; wires (electric); engineering change; functional change; resource allocation; resource constraints; spare cell selection; technology remapping; wire length; wirelength consideration; wiring cost estimate method; wiring cost measurement; Adders; Cost function; Length measurement; Logic functions; Process design; Resource management; Routing; Very large scale integration; Wire; Wiring;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537091