Space Compactor Design in VLSI Circuits Based on Graph Theoretic Concepts

The realization of space-efficient support hardware for built-in self-testing (BIST) is of great significance in VLSI circuits design. New approaches to designing aliasing-free space compaction hardware are proposed in the subject paper for testing cores-based system-on-chip (SOC) for single stuck-line faults, extending the well-known concepts of conventional switching theory, viz. those of cover table, frequency ordering commonly utilized in the simplification of switching functions, and of incompatibility relation to generate maximal compatibility classes using graph theoretic concepts, based on optimal generalized sequence mergeability, as developed by the authors in earlier works. The paper provides briefly the mathematical basis of selection criteria for merger of an optimal number of outputs of the circuit under test (CUT) to achieve maximum compaction ratio in the design, along with some partial simulation results on ISCAS 85 combinational benchmark circuits with programs ATALANTA and FSIM. The advantages of the suggested approaches are evident in achieving zero aliasing without any CUT modifications, while keeping the area overhead and signal propagation delay relatively low, besides their applicability with both deterministic compacted and pseudorandom test patterns