A compact carry-save multiplier architecture and its applications

Carry-save arithmetic based architectures are becoming popular in VLSI designs. However, few designs are available for 2´s complement carry-save multipliers. The carry-save outputs from conventional 2´s complement multipliers are not in legitimate carry-save form. This leads to errors if carry-save manipulations, such as, saturations, sign-extension etc are used. In this paper, a pure carry-save multiplier design is presented. The architecture is compact and regular leading to ease in VLSI implementation. This architecture is extended to design a carry-save multiplier/accumulator. By manipulating the partial product additions a row of adders are saved. Since multipliers form the basic building blocks of any signal processing ASIC design, this leads to large savings in chip area and power dissipation. Application of this design to equalizers and other signal processing blocks is also presented