Title :
Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations
Author :
Amerasekera, Ajith ; Ramaswamy, Sridhar ; Chang, Mi-Chang ; Duvvury, Charvaka
Author_Institution :
Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX, USA
fDate :
April 30 1996-May 2 1996
Abstract :
A circuit-level simulator for ESD and EOS is presented. Equations for modeling the high current behavior of NMOS and PMOS transistors have been developed and implemented in SPICE. A simple and practical extraction methodology for obtaining the bipolar parameters is given, which uses the three terminal currents obtained from a single high current I-V curve. Simulation results are presented and compared to experimental data for single devices as well as a practical output circuit.
Keywords :
CMOS integrated circuits; MOSFET; SPICE; avalanche breakdown; circuit analysis computing; electrostatic discharge; equivalent circuits; semiconductor device models; EOS; MOS snapback; NMOS transistors; PMOS transistors; SPICE; bipolar parameters; circuit-level ESD simulation; circuit-level simulator; high current I-V curve; high current simulations; parasitic bipolar action; Circuit simulation; Earth Observing System; Electrostatic discharge; Equations; Internal stresses; MOSFETs; Protection; SPICE; Semiconductor process modeling; Voltage;
Conference_Titel :
Reliability Physics Symposium, 1996. 34th Annual Proceedings., IEEE International
Conference_Location :
Dallas, TX, USA
Print_ISBN :
0-7803-2753-5
DOI :
10.1109/RELPHY.1996.492137
