Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data

We propose a methodology that employs boolean minimization and optimized test covering to identify redundant tests of a mixed-signal circuit from its pass-fail (binary) test data. This methodology is applied to two in-production circuits, a high-speed serializer/deserializer (HSS) and a phase-locked loop (PLL). Application of the methodology to over 38, 000 failing HSS circuits demonstrate that only 0.016% of them are mispredicted when three of nine high- voltage HSS tests are eliminated. Similarly, analysis of 22, 000 failing PLL circuits results in an error of 0.032% when 11 out of the 36 PLL tests are eliminated. Assuming 90% yield, these misprediction levels for the HSS and the PLL designs are equivalent to 16 and 32 DPM, respectively. The cost savings from eliminating the redundant tests in the HSS and the PLL designs at 90% yield are however estimated to be 21.9% and 30.9%, respectively.