Automatic circuit adjustment technique for process sensitivity reduction and yield improvement

In deep submicron process, parametric yield loss due to process variations has become a critical issue, especially for sensitive analog circuits. Design centering is one of the popular techniques to find the nominal design that leads to the maximum yield. However, in critical cases, it is possible that some parts of the performance distribution are still outside the feasible region and has no way to further improve the yield. Therefore, a process sensitivity reduction flow for analog circuits is proposed in this paper. Without moving the given nominal point, a new set of device sizes that lead to smaller performance distribution range can be obtained in the proposed sizing flow, which helps to further improve the yield of that design.