DocumentCode :
3373600
Title :
Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults
Author :
Sethuram, Rajamani ; Bushnell, Michael L. ; Agrawal, Vishwani D.
Author_Institution :
Design Autom. Group, Qualcomm, San Diego, CA
fYear :
2008
fDate :
April 27 2008-May 1 2008
Firstpage :
329
Lastpage :
335
Abstract :
This paper presents a new fault node for implication graph that represents the Boolean detectability status of a fault in the circuit. An implication graph with fault nodes is termed functional fault graph (FFG) because such a graph stores both the functional information and the fault information of the circuit. By computing the transitive closure and graph condensation of the FFG of a circuit, we show that we can collapse faults, and identify untestable faults and independent fault pairs in the circuit. Compared to prior fault independent-based approaches for fault collapsing, our technique gives the best result by reducing the fault-set size by 66%. Additional advantages of our technique compared to previous techniques are: a) It can also identify independent fault pairs in the circuit, and b) It can be extended for other fault models and has a variety of applications. Our experiment with c7552 also found more than 268 K independent fault pairs. This work also introduces the first fault-independent polynomial-time approach for identifying untestable transition delay faults.
Keywords :
Boolean algebra; circuit reliability; graph theory; logic gates; polynomials; Boolean detectability status; equivalence-dominance collapse; fault collapse; fault-independent polynomial-time approach; functional fault graph; functional information; independent-based approaches; transition delay faults; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Fault diagnosis; Polynomials; Test pattern generators; Very large scale integration; ATPG; Diagnosis; Fault Collapsing; Fault Model; Implication Graph;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2008. VTS 2008. 26th IEEE
Conference_Location :
San Diego, CA
ISSN :
1093-0167
Print_ISBN :
978-0-7695-3123-6
Type :
conf
DOI :
10.1109/VTS.2008.20
Filename :
4511745
Link To Document :
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