Title :
A configuration-speed acceleration method for a sequential circuit using a negative logic implementation
Author :
Moriwaki, Retsu ; Watanabe, Minoru
Author_Institution :
Electr. & Electron. Eng., Shizuoka Univ., Hamamatsu, Japan
Abstract :
An optically reconfigurable gate array (ORGA) was developed recently as one multi-context device to achieve high-speed reconfiguration. Since quick context switching allows implementation of many functions onto a gate array without idle time, fast reconfiguration is extremely important for multi-context devices. In ORGAs, the easiest way to increase the reconfiguration frequency is to use high-power lasers, but such lasers increase the ORGA power consumption and package size. In some cases, they might even require a cooling system. For that reason, this paper presents a configuration speed acceleration method for a sequential circuit using a negative logic implementation without ORGA architecture modification and without any increase of laser power. Based on experimentally obtained results, this paper clarifies the acceleration method´s effectiveness.
Keywords :
sequential circuits; ORGA architecture; configuration-speed acceleration; context switching; cooling system; high-power lasers; high-speed reconfiguration; multicontext devices; negative logic implementation; optically reconfigurable gate array; package size; power consumption; sequential circuit; Clocks; Context; Holographic optical components; Holography; Integrated optics; Lenses; Logic gates;
Conference_Titel :
Space Optical Systems and Applications (ICSOS), 2011 International Conference on
Conference_Location :
Santa Monica, CA
Print_ISBN :
978-1-4244-9686-0
DOI :
10.1109/ICSOS.2011.5783670