Realization of high-speed InP SHBTs using novel but simple techniques for parasitic reduction

We have developed novel but simple process techniques for high speed InP SHBTs. For parasitic reduction, the collector layer is undercut using etch-stop layer, base pad is isolated, and emitter metal is widened using thick plated gold. Typical common emitter dc current gain (β) and BV_CEO are about 25 and above 3.5 V, respectively at a collector current density of 1 × 10⁵ A/cm². Maximum extrapolated f_max of 450 GHz with f_τ of 215 GHz is achieved for 0.5 × 8 μm² emitter area devices at I_c= 17 mA and V_CE = 1.5 V. These data clearly show that the optimized conventional process can offer the direct implementation of InP HBT for high-speed electronic circuit fabrication.