Title :
Log-Domain Time-Multiplexed Realization of Dynamical Conductance-Based Synapses
Author :
Yu, Theodore ; Cauwenberghs, Gert
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of California San Diego, La Jolla, CA, USA
fDate :
May 30 2010-June 2 2010
Abstract :
We present a compact circuit architecture for analog VLSI realization of event-addressable neuromorphic arrays with conductance-based synaptic dynamics. Synaptic input events are time-multiplexed, pooled by synapse type according to common reversal potential and activation dynamics. One such physical synapse element per postsynaptic neuron is provided for each type, selected by type index along with postsynaptic address. A log-domain encoding of first-order linear dynamics of synaptic conductance results in a compact circuit realization with three MOS transistors per synapse element. Circuit simulations show low-power operation with linear dynamics in conductance.
Keywords :
VLSI; analogue integrated circuits; low-power electronics; neural nets; MOS transistors; activation dynamics; analog VLSI realization; conductance-based synaptic dynamics; event-addressable neuromorphic arrays; log-domain encoding; postsynaptic neuron; Circuit simulation; Encoding; MOSFETs; Neuromorphics; Neurons; Very large scale integration;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537114
