A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions

This paper presents an innovative approach for the generation of functional programs to test path- delay faults within microprocessors. The proposed method takes advantage of both the gate- and RT-level description of the processor. The former is used to build binary decision diagrams (BDDs) for deriving fault excitation conditions; the latter is exploited for the automatic generation of test programs able to excite and propagate fault effects, based on an evolutionary algorithm and fast RTL simulation. Experimental results on a simple microcontroller show that the proposed methodology is able to generate suitable test sets in reduced times.