Title :
An Industrial Case Study of Sticky Path-Delay Faults
Author :
Huang, I-De ; Chang, Yi-Shing ; Gupta, Sandeep K. ; Chakravarty, Sreejit
Author_Institution :
Intel Corp., Folsom, CA
fDate :
April 27 2008-May 1 2008
Abstract :
Sticky path-delay faults are path delay faults that are neither robustly nor non-robustly testable, but cannot be proven functionally unsensitizable. Better characterization of delay test quality requires a proper analysis of sticky path-delay faults. Furthermore, careful elimination of sticky path-delay faults contributes significantly to test development productivity and reduction of delay test cost. We present an industrial case study that shows the following, (a) On average, even after designers have removed false paths using automated tools and manual overrides, about 8% of path-delay faults with slack less than 10% of the clock period can be sticky, (b) Our approach, which extends a previously proposed technique, identifies a large subset of sticky path-delay faults that cannot cause functional failures and hence can be eliminated from further consideration. This significantly refines the delay test quality assessment and test development effort, (c) Our approach significantly reprioritizes (reorders) the remaining paths for test generation thereby improving the quality of the target path list.
Keywords :
automatic test pattern generation; delays; fault diagnosis; integrated circuit testing; automated tools; delay test quality; false paths; sticky path-delay faults; test generation; Automatic test pattern generation; Circuit faults; Circuit testing; Clocks; Delay; Fabrication; Robustness; System testing; Timing; Very large scale integration; delay testing; path reprioritization; sticky paths; test quality; timing false paths;
Conference_Titel :
VLSI Test Symposium, 2008. VTS 2008. 26th IEEE
Conference_Location :
San Diego, CA
Print_ISBN :
978-0-7695-3123-6
DOI :
10.1109/VTS.2008.44