A multiplierless structure for direct digital IF signal synthesis

Author

Huang, Ruimin ; Lotze, Niklas ; Becker, Markus ; Manoli, Yiannos

Author_Institution

Dept. of Microsyst. Eng. (IMTEK), Univ. of Freiburg, Freiburg, Germany

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

2530

Lastpage

2533

Abstract

A multiplierless structure using an 8th order band pass (BP) sigma delta (Σ△) modulator for synthesizing the intermediate frequency (IF) signal is presented in this paper. A fractional delay interpolation filter combining cascaded integrator-comb (CIC) and Lagrange filters is used before the Σ△-modulators to suppress the image caused by the time-interleaving in the IQ-paths. Closed form formulas for estimating the image suppression ratio (ISR) of different order interpolations are given. The results from the numeric analysis match the estimation well. The proposed structure has been implemented in an FPGA. The implementation results in 70dB image suppression for a band width of 1.56MHz at 25MHz center frequency.

Keywords

delay filters; direct digital synthesis; interpolation; sigma-delta modulation; signal synthesis; band pass sigma delta modulator; cascaded integrator comb; direct digital IF signal synthesis; fractional delay interpolation filter; frequency 1.56 MHz; frequency 25 MHz; image suppression ratio; intermediate frequency signal; multiplierless structure; Band pass filters; Delta-sigma modulation; Digital modulation; Field programmable gate arrays; Filtering; Frequency; Image sampling; Interpolation; Lagrangian functions; Signal synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537124

Filename

5537124