Title :
Synthesis of VHDL arrays on RAM cells
Author :
Berthet, C. ; Rampon, J. ; Sponga, L.
Author_Institution :
Thomson Composants Militaires et Spatiaux, St-Egreve, France
Abstract :
The problem of array objects in VHSIC hardware description language (VHDL) specifications for synthesis is considered. Experience shows that circuits obtained by synthesis tools are not as efficient as RAM macrocells. A new synthesis method is proposed that consists in mapping a VHDL array to a RAM primitive, together with a modification of the specification. The primitive is then mapped to a RAM generator of the THOMSON-TMS CSAM Library
Keywords :
circuit CAD; random-access storage; specification languages; RAM cells; THOMSON-TMS CSAM Library; VHDL arrays; VHSIC hardware description language; array objects; specifications; Arithmetic; Circuit synthesis; Clocks; Encoding; Flip-flops; Humans; Indexing; Libraries; Logic gates; Macrocell networks;
Conference_Titel :
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-2780-8
DOI :
10.1109/EURDAC.1992.246183
