Towards a standard VHDL synthesis package

The VHSIC hardware description language (VHDL) Synthesis Special Interest Group (SSIG) has been working on the development of a standard VHDL package for synthesis. The efforts of the group have been divided into four different areas: logic type, representation of numeric types, specification of constraints, and special identifications. Each of these areas addresses an important part of the information required for synthesis of a VHDL model. An important decision of the group was to adopt the std _logic type defined in the IEEE std _logic 1164 package. The numeric types area was created in order to provide arithmetic capabilities based on the std _logic value. The constraints area addresses design information beyond the functionality of the design that is still part of the specification. The special identifications area is a catch-all area for additional information about a design that may be useful to different aspects of the synthesis process