• DocumentCode
    3374112
  • Title

    VHDL intermediate format standardization activity: status and trends

  • Author

    Fonkoua, Alain ; Rouillard, Jacques

  • Author_Institution
    IMT Technopole de Chateau-Gombert, Marseille, France
  • fYear
    1992
  • fDate
    7-10 Sep 1992
  • Firstpage
    687
  • Lastpage
    688
  • Abstract
    The VIFASG is a Design Automation Standards Subcommittee (DASS) subgroup which was setup to develop a proposal for a standard intermediate format representation of VHSIC hardware description language (VHDL) models. The status of the current proposal and the remaining issues to be addressed are summarized
  • Keywords
    circuit CAD; specification languages; standardisation; Design Automation Standards Subcommittee; VHDL intermediate format standardization; VHSIC hardware description language; VIFASG; Debugging; Design optimization; Proposals; Standardization; Tree data structures;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
  • Conference_Location
    Hamburg
  • Print_ISBN
    0-8186-2780-8
  • Type

    conf

  • DOI
    10.1109/EURDAC.1992.246189
  • Filename
    246189
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3374112