Statistical delay modeling of read operation of SRAMs due to channel length variation

In this paper, we present a statistical modeling for the transition time of the static random-access memories during the read operation in the presence of the channel length variation. To model the I-V characteristics of the transistors, the a-power law model which is a simple analytical MOS model is used. To increase the accuracy, the effects of the short channel lengths as well as the drain bias are included in the modeling. The statistical analytical modeling is achieved by taking the partial derivations of the transition time expression. To assess the accuracy of the technique, HSPICE Monte-Carlo simulations have been used for a 65nm CMOS technology. The comparison, which is performed for different correlation coefficients, shows a very good accuracy for the model which is evaluated at substantially lower runtime.