BSIM4.1 DC parameter extraction on 50 nm n-pMOSFETs

Author

Souil, D. ; Guegan, G. ; Bertrand, G. ; Faynot, O. ; Deleonibs, S. ; Ghibaudo, G.

Author_Institution

Lab. d´´Electronique et des Technol. de l´´Inf., Grenoble, France

fYear

2002

fDate

8-11 April 2002

Firstpage

115

Lastpage

119

Abstract

For the first time, DC characteristics of conventional 50 nm MOSFETs have been correctly simulated by a BSIM4.1 model. This paper briefly describes the conventional architecture of the devices, and then the related strategy for parameter extraction is depicted. Typical simulation results are shown, illustrating that reverse short channel and 2D charge sharing effects are well fitted by this compact model.

Keywords

MOSFET; circuit simulation; semiconductor device models; 1.5 V; 2D charge sharing effects; 50 nm; 50 nm n-pMOSFETs; BSIM4.1 DC parameter extraction; DC characteristics; MOSFET architecture; circuit simulations; compact model; drain current; gate currents; parameter extraction strategy; reverse short channel effects; saturation currents; simulation results; Circuit optimization; Data mining; Leakage current; MOSFET circuits; Optimized production technology; Parameter extraction; Quantum capacitance; Semiconductor device modeling; Semiconductor process modeling; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2002. ICMTS 2002. Proceedings of the 2002 International Conference on

Print_ISBN

0-7803-7464-9

Type

conf

DOI

10.1109/ICMTS.2002.1193182

Filename

1193182