Spike based learning with weak multi-level static memory

In this paper we present a VLSI implementation of learning synapse that that uses a spike based learning rule to adjust its weight. The weight is stored on a recently presented weak multi-level static memory cell (MLSM) by Hafliger and Riis (see ibid., May 2003). This memory cell stores a voltage on a capacitance and that voltage is weakly driven to the closest of several stable levels. We verified the suitability of this memory for this task in a VLSI chip implementation. An array of integrate and fire neurons with four of these learning synapse each was implemented on a 0.6 μm AMS CMOS chip. The learning capability of these neurons was tested in simple spike and rate based pattern recognition tasks in a two neuron network. Cross-inhibition between them lead to improved decorrelation of the output spikes, inducing a tendency in the neurons to specialize on different patterns.