Influence of probing configuration and data set size for bipolar junction capacitance determination

Author

Macsweeney, D. ; McCarthy, K.G. ; Floyd, L. ; Mathewson, A. ; Hurley, P. ; Power, J.A. ; Kelly, S.C.

Author_Institution

Cypress Semicond., Cork, Ireland

fYear

2002

fDate

8-11 April 2002

Firstpage

127

Lastpage

132

Abstract

In this paper, the on-wafer measurement of junction depletion capacitance is examined. This work provides an in-depth discussion of possible probing configurations which can be used. It outlines a method to consistently measure the junction capacitances accurately. The results from this method compare favourably with those extracted using S-parameter measurements. Additionally a method is formulated to determine the minimum number of data points required to maintain extraction accuracy.

Keywords

S-parameters; bipolar transistors; capacitance measurement; semiconductor device measurement; semiconductor device models; S-parameter measurements; bipolar circuit simulations; bipolar devices; bipolar junction capacitance determination; bootstrap technique; consistent junction capacitance measurement; data set size; extraction accuracy; minimum number of data points; on-wafer measurement; probing configuration; Capacitance measurement; Carbon capture and storage; Cutoff frequency; Educational institutions; Logic circuits; Logic devices; Parasitic capacitance; Propagation delay; Scattering parameters; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2002. ICMTS 2002. Proceedings of the 2002 International Conference on

Print_ISBN

0-7803-7464-9

Type

conf

DOI

10.1109/ICMTS.2002.1193184

Filename

1193184