Title :
1992 VHDL standardization overview
Abstract :
The author reports on the VHSIC hardware description language (VHDL) standardization process. A brief description is given of language design objectives, areas of language change, language documentation, language validation, modeling, simulation, synthesis and upward compatibility
Keywords :
Accuracy; Circuit synthesis; Circuit testing; Delay; Documentation; Hardware design languages; Scheduling; Standardization; Steady-state; Timing;
Conference_Titel :
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-2780-8
DOI :
10.1109/EURDAC.1992.246197
