DocumentCode
3374271
Title
1992 VHDL standardization overview
Author
Shahdad, Moe
fYear
1992
fDate
7-10 Sep 1992
Firstpage
666
Lastpage
667
Abstract
The author reports on the VHSIC hardware description language (VHDL) standardization process. A brief description is given of language design objectives, areas of language change, language documentation, language validation, modeling, simulation, synthesis and upward compatibility
Keywords
Accuracy; Circuit synthesis; Circuit testing; Delay; Documentation; Hardware design languages; Scheduling; Standardization; Steady-state; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location
Hamburg
Print_ISBN
0-8186-2780-8
Type
conf
DOI
10.1109/EURDAC.1992.246197
Filename
246197
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