Title :
A signed spatial contrast event spike retina chip
Author :
Leñero-Bardall, J.A. ; Serrano-Gotarredona, T. ; Linares-Barranco, B.
Author_Institution :
Inst. de Microelectron. de Sevilla (IMSE-CNM-CSIC), Sevilla, Spain
fDate :
May 30 2010-June 2 2010
Abstract :
Reported AER (Address Event Representation) contrast retinae perform a contrast computation based on the ratio between a pixel´s local light intensity and a spatially weighted average of its neighbourhood. This results in compact circuits, but with the penalty of all pixels generating output signals even if they sense no contrast. In this paper we present a spatial contrast retina with bipolar output: contrast is computed as the relative normalized difference (not the ratio) between a pixel´s local light and its weighted spatial average, normalized to average light. As a result, contrast includes a sign, is ambient light independent, and the output will be zero if there is no contrast. Furthermore, an adjustable thresholding mechanism has been included, such that pixels remain silent until they sense an absolute contrast above the adjustable threshold. The pixel contrast computation circuit is based on Boahen´s Biharmonic operator contrast circuit, which has been improved to include mismatch calibration and adaptive current based biasing. As a result, the contrast computation circuit shows much less mismatch, is almost insensitive to ambient light illumination, and biasing is much less critical than in the original voltage biasing scheme. The retina also includes an optional TFS (Time-to-First-Spike) integration mode. A full AER retina version has been fabricated and tested. In the present paper we provide preliminary experimental results.
Keywords :
CMOS integrated circuits; calibration; image recognition; Boahen Biharmonic operator contrast circuit; CMOS process; adaptive current based biasing; address event representation; calibration; mismatch calibration; spatial contrast retina; spatially weighted average; Retina;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537152