SYNTEST: an environment for system-level design for test

Author

Harmanani, H. ; Papachristou, C. ; Chiu, S. ; Nourani, M.

Author_Institution

Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA

fYear

1992

fDate

7-10 Sep 1992

Firstpage

402

Lastpage

407

Abstract

The authors describe the design and implementation of SYNTEST, a system for the design of self-testable VLSI circuits from behavioral description. SYNTEST consists of several algorithmic synthesis tools for scheduling, testable allocation, and optimum test points selection. A key feature in SYNTEST is the tight interaction between the system tools: the scheduler, the allocator, and the test tool. The system uses a technology library for optimizing the original structure. All tools interact with each other as well with the user through an X graphical interface. This provides a better design environment and allows for more designer intervention

Keywords

VLSI; automatic testing; design for testability; graphical user interfaces; integrated circuit testing; scheduling; SYNTEST; X graphical interface; algorithmic synthesis tools; allocator; behavioral description; design environment; optimum test points selection; scheduling; self-testable VLSI circuits; system-level design for test; technology library; testable allocation; Built-in self-test; Circuit synthesis; Circuit testing; High level synthesis; Logic design; Logic testing; Process design; System testing; System-level design; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Conference_Location

Hamburg

Print_ISBN

0-8186-2780-8

Type

conf

DOI

10.1109/EURDAC.1992.246212

Filename

246212