• DocumentCode
    3374575
  • Title

    Generating pipelined datapaths using reduction techniques to shorten critical paths

  • Author

    Lobo, Donald A. ; Pangrle, Barry M.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
  • fYear
    1992
  • fDate
    7-10 Sep 1992
  • Firstpage
    390
  • Lastpage
    395
  • Abstract
    A new approach to pipelined scheduling is demonstrated. Using a greedy algorithm to generate the initial solution and then applying a series of transformations to the graph is shown to be effective in obtaining optimal and near optimal results without resorting to an exhaustive search. The algorithm handles multicycle pipelined functional units leading to the generation of compact schedules. Using pipelined functional units, the effective throughput is increased and shorter latency times are produced. Thus, in the case of the optimized finite impulse response (FIR) filter, a throughput of three clock cycles, with a latency of nine clock cycles can be obtained using a functional unit specification of five one-cycle adders and three two-cycle pipelined multipliers. In this case the throughput is doubled, and the latency is improved by 33% using pipelined units over non-pipelined units
  • Keywords
    adders; circuit CAD; digital filters; multiplying circuits; critical paths; greedy algorithm; latency; latency times; multicycle pipelined functional units; one-cycle adders; optimised FIR filters; pipelined datapaths; pipelined multipliers; reduction techniques; Circuits; Clocks; Computer science; Design engineering; Libraries; Partitioning algorithms; Pipeline processing; Processor scheduling; Registers; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
  • Conference_Location
    Hamburg
  • Print_ISBN
    0-8186-2780-8
  • Type

    conf

  • DOI
    10.1109/EURDAC.1992.246214
  • Filename
    246214