A robust and production worthy addressable array architecture for deep sub-micron MOSFET´s matching characterization

Author

Yeo, S.B. ; Bordelon, J. ; Chu, S. ; Li, M.-F. ; Tranchina, B.A. ; Harward, M. ; Chan, L.H. ; See, A.

Author_Institution

Nat. Univ. of Singapore, Singapore

fYear

2002

fDate

8-11 April 2002

Firstpage

229

Lastpage

234

Abstract

A robust addressable array test structure is presented, which allows automated characterization of the MOSFET´s matching, with high area and time efficiency, accuracy and repeatability. It features CMOS switches to ensure a full test operation range, and prevent gate oxide breakdown of individual DUTs from destroying the functionality of the whole test structure. The test structure provides superior isolation to minimize cross talk while providing greater flexibility in testing. The testing result (Id mismatch) on wafers of 0.18 μm technology is presented.

Keywords

CMOS integrated circuits; MOSFET; VLSI; arrays; integrated circuit testing; production testing; 0.18 micron; CMOS switches; MOSFET matching characterization; automated characterization; crosstalk minimization; deep submicron MOSFETs; gate oxide breakdown; manufacturing environment; production worthy addressable array architecture; robust addressable array architecture; test structure; volume test methodology; CMOS technology; Circuit testing; Electric breakdown; Kelvin; MOSFET circuits; Probes; Production; Robustness; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2002. ICMTS 2002. Proceedings of the 2002 International Conference on

Print_ISBN

0-7803-7464-9

Type

conf

DOI

10.1109/ICMTS.2002.1193201

Filename

1193201