A 39×48 general-purpose focal-plane processor array integrated circuit

Author

Dudek, Piotr

Author_Institution

Dept. of Electr. Eng. & Electron., Univ. of Manchester Inst. of Sci. & Technol., UK

Volume

5

fYear

2004

fDate

23-26 May 2004

Abstract

This work presents the implementation of a general-purpose programmable vision chip, with a 39×48 SIMD processor-per-pixel array, fabricated in a 0.35 μm CMOS technology. The chip employs analogue processing elements to achieve cell density of 410 cells/mm². The array operates at 1.25 MHz with power consumption of 12 μW/cell and executes low-level image-processing algorithms in real time. Chip architecture, circuit and layout design issues are discussed. Experimental results are presented.

Keywords

CMOS integrated circuits; analogue processing circuits; image processing; integrated circuit layout; microprocessor chips; programmable circuits; 0.35 micron; 1.25 MHz; CMOS technology; SIMD processor-per-pixel array; analogue processing elements; cell density; chip architecture; circuit layout design; focal-plane processor array; integrated circuits; low-level image-processing; programmable vision chip; real time processing; Arithmetic; CMOS integrated circuits; CMOS process; CMOS technology; Energy consumption; Gray-scale; Image processing; Integrated circuit technology; Logic design; Photodetectors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329615

Filename

1329615