DocumentCode
3374711
Title
Enhancing online error detection through area-efficient multi-site implications
Author
Alves, N. ; Shi, Y. ; Dworak, J. ; Bahar, R.I. ; Nepal, K.
Author_Institution
Sch. of Eng., Brown Univ., Providence, RI, USA
fYear
2011
fDate
1-5 May 2011
Firstpage
241
Lastpage
246
Abstract
We present a new method to identify multi-site implications that can significantly increase the fault coverage of error-detecting hardware without increasing the area overhead. This method intelligently divides the input space about the functions of internal circuit sites and finds new valuable implications that can share gates in checker logic.
Keywords
error detection; fault location; logic circuits; area-efficient multi site implications; checker logic; error-detecting hardware; fault coverage; input space; internal circuit sites; online error detection; Benchmark testing; Delay; Electrical fault detection; Hardware; Integrated circuit modeling; Logic gates;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium (VTS), 2011 IEEE 29th
Conference_Location
Dana Point, CA
ISSN
1093-0167
Print_ISBN
978-1-61284-657-6
Type
conf
DOI
10.1109/VTS.2011.5783728
Filename
5783728
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