A new low power building block cell for adders

Author

Sayed, A. ; Bayoumi, M.

Author_Institution

Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA

Volume

2

fYear

1997

fDate

3-6 Aug 1997

Firstpage

818

Abstract

One of the main factors in developing low power systems is reducing power consumption at the circuit design level and the module building block levels in the design. Following this strategy a low power and high speed full adder cell with the minimum number of transistors has been developed. The proposed cell is a combination of a 3-input XOR gate and transmission gates. The proposed cell has been compared to the other three basic common cells. An extensive analysis of the four architectures of adders, namely carry ripple, carry skip, carry select and carry lookahead has proved the superiority of the proposed cell

Keywords

CMOS logic circuits; adders; carry logic; logic design; logic gates; 3-input XOR gate; adder architectures; carry lookahead type; carry ripple type; carry select type; carry skip type; circuit design level; high speed full adder cell; low power building block cell; module building block level; power consumption reduction; transmission gates; Adders; CMOS logic circuits; Circuit synthesis; Computer architecture; Energy consumption; Logic gates; Mobile computing; Power system analysis computing; Power systems; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on

Conference_Location

Sacramento, CA

Print_ISBN

0-7803-3694-1

Type

conf

DOI

10.1109/MWSCAS.1997.662200

Filename

662200