Title :
Automatic module allocation in high level synthesis
Author :
Gutberlet, P. ; Müller, J. ; Krämer, H. ; Rosenstiel, W.
Author_Institution :
Forschungszentrum Inf., Karlsruhe, Germany
Abstract :
A main step in high-level synthesis is data-path synthesis consisting of allocation, scheduling and assignment. The authors present an allocation algorithm designed for an environment where the allocation precedes scheduling and assignment. This algorithm selects the hardware components (in type and number) fully automatically and supports a realistic area/time tradeoff. During this allocation a design space exploration is performed. The allocation is separated from the scheduling and assignment, allowing very efficient implementation
Keywords :
VLSI; circuit CAD; scheduling; VLSI; assignment; automatic module allocation; design space exploration; hardware components; high level synthesis; scheduling; Adders; Algorithm design and analysis; Circuit synthesis; Clocks; Hardware; High level synthesis; Integrated circuit synthesis; Scheduling algorithm; Space exploration; Timing;
Conference_Titel :
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-2780-8
DOI :
10.1109/EURDAC.1992.246223
