Structural tests of slave clock gating in low-power flip-flop

A novel slave clock-gating technique in Naffziger, 2010 is designed to save power when the master and slave latches of a low-power flip-flop reach certain correlated states (e.g., both latches are at logic 0 or 1). Testing this clock-gating circuit is essential for power-sensitive applications, but is also very challenging. This is because power consumption increase is its only defective behavior, and it involves cell internal states, both of which are unfriendly to general automatic test-pattern generation (ATPG). This paper proposes an innovative method to test the slave clock-gating circuitry structurally with slight modification of the flop cell. The implementation on a two-latch version of a level-sensitive scan design (LSSD) flip-flop and its capability of extending to other types of flip-flop cells are presented.