Title :
A 100 µW Decimator for a 16 bit 24 kHz bandwidth Audio ΔΣ Modulator
Author :
Parameswaran, Shankar ; Krishnapura, Nagendra
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Chennai, India
fDate :
May 30 2010-June 2 2010
Abstract :
A decimation filter for a low power Delta Sigma (ΔΣ) modulator with 24 kHz bandwidth and an in band resolution of 16 bits is designed with standard cells in a 1.8 V, 0.18μm CMOS process. Retiming, Canonical Signed Digits (CSD) encoding along with optimal selection of data width are coded with a hardware description language (HDL) to obtain optimality for power and an automated design. The filter occupies an area of 0.46 mm2 and consumes 100μW from a supply of 1.8 V and is operational down to a supply voltage of 0.9 V. This makes it suitable for use with very low power ΔΣ data converters for digital audio.
Keywords :
CMOS digital integrated circuits; delta-sigma modulation; digital filters; hardware description languages; low-power electronics; CMOS process; HDL; audio ΔΣ modulator; bandwidth 24 kHz; canonical signed digits encoding; decimation filter; digital audio; hardware description language; low power delta sigma modulator; power 100 muW; size 0.18 mum; very low power data converters; voltage 0.9 V; voltage 18 V; Band pass filters; Bandwidth; CMOS technology; Delta modulation; Digital modulation; Encoding; Finite impulse response filter; Hardware design languages; Noise shaping; Quantization;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537170
