Design for Bit Error Rate estimation of high speed serial links

High speed serial links, consisting of SerDes devices, require the Bit Error Rate (BER) to be at the level of 10^-12 or lower. The excessive test time for comparing each captured bit for error detection in the traditional BER measurement and the costly instrumentation are major drawbacks for high volume production test of SerDes devices. In this paper, we propose a design for BER estimation methodology which includes a new BER estimation method, a simple BER test system which incorporates a novel design of time-to-digital converter (TDC).