Design of A Novel Asynchronous Reconfigurable Architecture for Cryptographic Applications

Cryptographic algorithms are usually compute-intensive and more efficiently implemented in hardware than in software running on general-purpose processors. However, systems which use hardware implementations have significant drawbacks: they are unable to respond to flaws discovered in the implemented algorithm or to changes in standards. By taking advantage of FPGA technology, some work offers high performance and flexible solutions for cryptographic algorithms. But FPGAs still have some drawbacks. To overcome these shortages of FPGA, such as redundant routing resources which increase chip area and power consumption, a novel asynchronous reconfigurable cryptographic engine (ARCEN) is introduced. In this architecture, reconfigurable cryptographic array is the kernel. It routes signals asynchronously between adjacent cells through neighbor-to-neighbor wires with 4-phase handshaking protocol. Computation circuit for reconfigurable cell is developed with modified DSDCVS logic. On the implementation of cryptographic algorithms such as AES, the architecture shows a better performance than FPGA