Minimal area merger of finite state machine controllers

The authors present techniques for merging a pair of finite state machines (FSMs) that control the data-path circuitry on a chip. In particular, these techniques can be used to merge FSMs that control the functional and test circuitry in the data path. An A* algorithm is used to obtain the state transition table of the merged controller, and then standard synthesis tools are used for state assignment and logic minimization. The procedure targets either two-level or multilevel logic implementation. Compared to implementing the functional and test controllers separately, it is shown that merging the controllers leads to significant savings in logic area. For multilevel implementation, the technique produces merged machines that have on average 20% less factored form literals than the machines produced by an existing state minimizer