DocumentCode
3375039
Title
Challenges raised by long on-chip wiring for CMOS microprocessor applications
Author
Deutsch, A. ; Kopcsay, G.V. ; Surovic, C.W. ; Rubin, B.J. ; Terman, T.M. ; Dunne, R.P. ; Gallo, T.
Author_Institution
Res. Div., IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
1995
fDate
2-4 Oct 1995
Firstpage
21
Lastpage
23
Abstract
The unique characteristics of long on-chip interconnections in terms of modelling, simulation and design practices are investigated for representative five-layer structures. Experimental results are shown for a specially designed test vehicle with lines as long as 1.6 cm and line resistance of R=35 to 500 Ω/cm
Keywords
CMOS digital integrated circuits; integrated circuit interconnections; microprocessor chips; 1.6 cm; CMOS microprocessor; design; five-layer structure; interconnections; modelling; on-chip wiring; simulation; Capacitance; Crosstalk; Delay; Frequency; Integrated circuit interconnections; Microprocessors; Power transmission lines; Propagation losses; Testing; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 1995
Conference_Location
Portland, OR
Print_ISBN
0-7803-3034-X
Type
conf
DOI
10.1109/EPEP.1995.524683
Filename
524683
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