Detailed analyses in prediction of capacitive-mismatch-induced offset in dynamic comparators

Due to the positive feedback and the time varying clock signal, the operating point of each transistor in dynamic comparators is time varying and cannot be analyzed using traditional Op-Amp-based small signal analysis. Until recently, a balanced method is proposed to effectively get the analytical models for random offset caused by variations in process parameters. Meanwhile, it has been shown that mismatches from parasitic capacitors are also significant contributors to overall offset. However, the energy storage and nonlinear feature of capacitor make it even more challenging to analytically predict the capacitive mismatch induced offset. In this work, the previous proposed balance method is generalized and applied to tackle the problem of capacitive mismatch induced offset. The analytical models are derived to explicitly show offsets caused by capacitor mismatch at different internal nodes. The insights are obtained on identifying the sensitive nodes to capacitor mismatch and on how to reduce the offset. The numerical example validates the effectiveness of the analytical models.