Title :
Cellular nanoscale network cell with memristors for local implication logic and synapses
Author :
Laiho, Mika ; Lehtonen, Eero
Author_Institution :
Microelectron. Lab., Univ. of Turku, Turku, Finland
fDate :
May 30 2010-June 2 2010
Abstract :
This paper describes a cellular nanoscale network cell structure that is aimed to be built as a CMOS-nanomemristor hybrid. The processing cell uses memristors as ON-OFF programmable synapses, local logic and memory. Local logic is based on memristor computations using material implication. Only 15 CMOS transistors per cell are used, independent of the size of the neighborhood, since memristors are used as synapses. Also, space-dependent templates (weight matrices) are possible at no extra hardware cost. The operation of the cell is described and simulation results are shown to illustrate the operation.
Keywords :
CMOS logic circuits; memristors; CMOS-nanomemristor hybrid; ON-OFF programmable CNN; cellular nanoscale network cell; local logic; space-dependent template; weight matrices; CMOS logic circuits; CMOS process; Cellular networks; Cellular neural networks; Hardware; Memristors; Microelectronics; Nanoscale devices; SPICE; Threshold voltage;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537188
