Exploiting rotational symmetries for improved stacked yields in W2W 3D-SICs

Three-dimensional Stacked Integrated Circuit packages interconnected using high speed Through-Silicon Via technology can be efficiently manufactured using a wafer-to-wafer stacking process. Efforts to mitigate degradation in the composite yield of the stacked die are primarily focused on matching defect maps while assigning the pre-tested wafers from the available wafer repository to individual wafer stacks. In this paper we show how rotational symmetry can be exploited to increase the number of available wafer defect maps by a factor of four, thereby significantly improving matching possibilities and hence yield. We further apply our approach to processor-memory stacks, with relatively high memory die yield from redundancy and repair, for which we also present new heuristic matching algorithms. Altogether, our new approach shows viable absolute yields, with yield improvement of better than 25% over stacking without any matching. This is a significant advance over earlier results.