Leakage power profiling and leakage power reduction using DFT hardware

In a CMOS logic circuit, the leakage power dissipated depends on the state of the design. In this paper we propose a novel technique to use the Q-gating logic that are added to reduce power during shift to also reduce leakage power during functional standby mode of the circuit. First, we propose leakage-aware test (λ-test) vector generation that can be used to profile leakage power consumed by the circuit. This is used to identify blocks that drains excessive standby leakage power. We also propose a new partial Q-gating technique that uses the λ-test to determine the subset of flops that should be gated-off to achieve maximum simultaneous reduction in shift mode dynamic power and standby mode leakage power. A fast, test relaxation and test cube merging algorithm is used for this purpose. Experiments conducted on ISCAS and ITC benchmarks show up to 43.6% reduction in leakage power. For the partial gated design, we obtained up to 15.3% leakage power reduction and up to 6.1× reduction in shift power.