Ant colony optimization for symmetrical FPGA placement

Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. This paper presents a method for symmetrical FPGA placement based on ant colony optimization (ACO). Also, we take the routing congestion into consideration by introducing a congestion factor in our algorithm. Experimental results show that compared with the state-of-the-art FPGA place and route tool VPR, ACO algorithm achieves promising performance, in terms of routing channel density.