Title :
Delay macromodels for the timing analysis of GaAs DCFL
Author :
Kayssi, Ayman I. ; Sakallah, Karem A.
Author_Institution :
Dept. of Electron. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Abstract :
A timing macromodel for gallium arsenide direct-coupled FET logic (GaAs DCFL) cells is derived. It calculates the delay of a cell as a function of such parameters as transistor sizes, capacitive loading, fanout, and input switching time. Calculations based on the derived macromodel show excellent agreement with circuit simulation at two to three orders of magnitude savings in computation time
Keywords :
III-V semiconductors; circuit analysis computing; delays; direct coupled FET logic; gallium arsenide; integrated logic circuits; GaAs DCFL; capacitive loading; circuit simulation; delay; direct-coupled FET logic; fanout; input switching time; timing analysis; timing macromodel; transistor sizes; Capacitance; Circuit analysis computing; Delay effects; Driver circuits; Gallium arsenide; Logic; Propagation delay; Switching circuits; Threshold voltage; Timing;
Conference_Titel :
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-2780-8
DOI :
10.1109/EURDAC.1992.246251
