Speed-up estimation for HW/SW-systems

Author

Hardt, Wolfram ; Rosenstiel, Wolfgang

Author_Institution

Paderborn Univ., Germany

fYear

1996

fDate

18-20 Mar 1996

Firstpage

36

Lastpage

43

Abstract

HW/SW-codesign has been applied to a wide range of applications. Several partitioning methods have been suggested. Thus the designer selects modules for HW or SW-implementation for the best possible performance within a set of performance and design constraints. This paper describes an estimation method to approximate a priori the entire system performance. The estimation method has been integrated into the codesign tool COD and first results could be generated. The estimated speed-up has been determined for a ciphering algorithm and has been compared to the speed-up of the entire HW/SW-system. The estimation speed-up matches the final speedup

Keywords

logic design; systems analysis; HW/SW-systems; ciphering algorithm; codesign tool COD; hardware/software codesign; partitioning methods; speed-up estimation; system performance; Acceleration; Computer architecture; Constraint optimization; Costs; Delay estimation; Design optimization; Flow graphs; Parameter estimation; System performance; Time factors;

fLanguage

English

Publisher

ieee

Conference_Titel

Hardware/Software Co-Design, 1996. (Codes/CASHE '96), Proceedings., Fourth International Workshop on

Conference_Location

Pittsburgh, PA

Print_ISBN

0-8186-7243-9

Type

conf

DOI

10.1109/HCS.1996.492224

Filename

492224