Case Study: Efficient SDD test generation for very large integrated circuits

Semiconductor industry has come to the era to rely heavily on detecting small-delay defects (SDDs) for high defect coverage of manufactured digital circuits and low defective parts per million (DPPM). Traditional timing-unaware transition-delay fault (TDF) ATPGs are proven to be inefficient in detecting SDDs. The commercial timing-aware ATPGs have been developed for screening SDDs, but they suffer from large pattern count and CPU runtime. The previously proposed methodologies are either inefficient or too complex in terms of memory and runtime to be applied to large industry designs (>;few million gates). In this paper, we present a new SDD-based pattern grading and selection procedure to meet the SDD test challenges in practice. We propose techniques to reduce the runtime and memory complexity and make the procedure applicable and scalable to large industry designs. Experimental results on both academic and industry circuits demonstrate the efficiency of our procedure; it detects a greater number of SDDs with a much lower pattern count and CPU runtime.