Title :
A framework for interactive analysis of timing constraints in embedded systems
Author :
Gupta, Rajesh K.
Author_Institution :
Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Abstract :
An important goal of embedded system co-synthesis is to realize system designs under constraints on timing performance. We present applicable constraints and the notion of satisfiability of a given set of constraints. We describe a two-level system model that is useful for carrying out constraint analysis in presence of the timing and execution uncertainty inherent in embedded systems. We conclude by presenting a framework to determine constraint satisfiability and to interactively debug constraint violations. Examples are presented to show the utility of our approach
Keywords :
computability; logic design; performance evaluation; real-time systems; timing; constraint satisfiability; embedded systems; interactive analysis; satisfiability; timing constraints; timing performance; Computer science; Embedded computing; Embedded system; Hardware design languages; Instruments; Performance analysis; Process control; System analysis and design; Timing; Uncertainty;
Conference_Titel :
Hardware/Software Co-Design, 1996. (Codes/CASHE '96), Proceedings., Fourth International Workshop on
Conference_Location :
Pittsburgh, PA
Print_ISBN :
0-8186-7243-9
DOI :
10.1109/HCS.1996.492225
