Efficient and product-representative timing model validation

Timing analysis is a key sign-off step in the design of today´s chips, but as technology advances, it becomes ever more challenging to create timing models that accurately reflect real timing-related behavior. Complex dependencies on second order phenomena, such as pattern density and stress/strain make it very difficult to develop device models and simulation tools that accurately predict the timing behavior that will be seen in actual product silicon. As a result, it is necessary to validate timing models in silicon. Traditional ways to validate timing models use ring oscillators or perform delay testing but both approaches have significant drawbacks. Ring oscillators lack diversity in circuit structure and present layout configurations that are not typical of real products. Delay test can be expensive to apply and provides directly only path delay information not individual gate delays. To address these limitations, we explore the potential of a new test structure-based method of timing model validation. The proposed approach combines benefits of a ring oscillator and path delay testing while addressing their limitations. Specifically, the test structure is composed of circuits that are physically synthesized and therefore product-representative, but configures the devices under test into oscillating paths so that measurement is easy and inexpensive. Path delay test ATPG is used to generate test patterns whose oscillation frequencies provide measures of path delays. Gate delays are deduced from those path delays using a matrix that codes the delay elements comprising each path in a careful way that overcomes overdetermination problems in the matrix algebra. Results show that RMS errors can be maintained under 5% for all gate types using a chosen circuit.